1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming embedded source/drain regions on FinFET devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, sidewall spacers 18 and a gate hard mask 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The direction of current travel when the device 10 is operational, i.e., the gate length (GL) of the device 10, corresponds to the direction of the axial length 14L of the fins 14. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10, while the portions of the fins 14 that are positioned outside of the spacers 18 are the source/drain regions of the device 10. The fins 14 are typically formed by performing an etching process through a patterned hard mask layer to define a plurality of fin-formation trenches 13 in the substrate 12 so as to define the fins 14. Thereafter, a layer of insulating material 22, e.g., silicon dioxide, is blanket-deposited across the substrate 12 such that it over-fills the trenches 13. Several process operations are performed (chemical mechanical polishing (CMP) and recess etching) so as to reduce the as-deposited thickness of the layer of insulating material 22 and thereby result in the recessed layer of insulating material 22 depicted in FIG. 1. The recessed layer of insulating material 22 has a recessed upper surface 22R that is at a desired height level within the trenches 13 so as to establish the final approximate fin height for the fins 14 of the device 10. Note that, in the typical prior art process flow, the layer of insulating material 22 is recessed within the trenches 13 prior to the formation of any materials for the gate structure 16.
Eventually, electrical contacts will be formed to contact the source/drain regions of the device 10. Ideally, the contact area in the source/drain regions will be as large as possible and exhibit as low an electrical contact resistance as possible. In some traditional process flows, additional epi semiconductor material may be formed on the portions of the fins 14 in the source/drain regions of the device 10 to facilitate making the formation of such contacts. There are various ways in which this epi semiconductor material may be formed. In one example, referred to as “unmerged epi,” the intent is to form a limited amount of epi semiconductor material on each of the individual fins without the epi material contacting epi material on adjacent fins. Some problems with this unmerged epi approach is that the volume of epi material that is formed on each fin is very limited due to the very tight fin pitch used in advanced devices, and the contact resistance tends to be higher than is desired due to the limited volume of epi material and the limited contact area. Another problem with the unmerged epi approach is that it is simply very difficult to only grow epi material on individual fins without contacting the epi material on adjacent fins because of the above-noted very small fin pitches used in advanced devices. Another approach is referred to as “merged epi.” As the name implies, in the merged epi approach, the epi material is grown such that the epi material on adjacent fins merges together so as to form a relatively larger contact area which produced a lower electrical contact resistance. One problem with the merged epi approach is that the epi semiconductor material, if not constrained or limited by other structures, may grow in areas where is it not desired. As a worst-case example, merged epi material on one device may grow laterally to such an extent that it unintentionally spans across an isolation region and contacts the active region or other epi material formed on an adjacent device, thereby creating a conductive path between the two devices that were intended to be electrically isolated from one another. Efforts to form structures that limit such undesirable lateral growth of the epi semiconductor material can involve many complex processing steps and increase the cost of production. Yet another approach that is sometimes employed when forming epi semiconductor material on the portions of the fins 14 that are positioned in the source/drain regions of a FinFET device is referred to as an “embedded epi.” In the embedded epi approach, after the fins 14 are formed, the portions of the fins positioned above the upper surface 22R of the layer of insulating material 22 are removed, i.e., the upper surface of the remaining portion of the fin is positioned at a level that is slightly below the surface 22R. Thereafter, epi semiconductor material is grown on this exposed upper surface of the remaining portion of the fin. In the embedded epi approach, the final epi material may be formed in an “unmerged” or “merged” condition.
The present disclosure is directed to novel methods of forming embedded source/drain regions on FinFET devices and the resulting devices that may solve or reduce one or more of the problems identified above.